One American National Standards Institute (ANSI) standard for synchronous data transmission on optical media is known as Synchronous Optical NETwork (SONET), and defines a hierarchy of Optical Carrier (OC) levels and electrically equivalent Synchronous Transport Signals (STSs) for an optical communications system. The international equivalent to SONET is Synchronous Digital Hierarchy (SDH). In contrast, Plesiosynchronous Digital Hierarchy (PDH) has traditionally been employed.
A SONET datastream is arranged in frames of nine equal-length segments. Each frame can be depicted as nine rows and 90 columns, each “cell” being one byte in length. Each SONET segment comprises 3 Transport Overhead (TOH) bytes. Consequently, the first three columns constitute TOH bytes comprising information regarding, for example, the frame's destination. The remaining columns constitute a Synchronous Payload Envelope (SPE) for carrying payload data such as voice, high speed data and video.
As mentioned above, the SONET standard defines OC levels and electrically equivalent STSs for the fibre-optic based transmission hierarchy. In order to carry many signals of different capacities through a single optical hierarchy, a byte-interleaved multiplexing scheme is used, which simplifies multiplexing and provides end-to-end network management. In order to multiplex, a lowest level, or base, signal must first be generated. The base signal is known as the STS Level-1 (STS-1/OC-1) and corresponds to a bit rate of 51.84 Mbits/s. Higher level signals can be generated from integer multiples of the byte-interleaved STS-1 signal, such as OC-3 (155.2 Mbps), OC-12 (622.08 Mbps) and OC-48 (2488.32 Mbps) The SONET STS-1 base signal can be built by multiplexing signals of a lower bit rate, such signals being known as tributaries. The individual tributaries can each carry a different payload having a separate destination. Furthermore, several SONET base signals can be multiplexed to form SONET signals having a higher bit rate as mentioned above.
When multiplexing individual tributaries of a lower bit rate to form a SONET STS-1 signal, it is often necessary to map the asynchronous bit rate of the tributary to the higher bit rate of the SONET STS-1 signal using bit justification or ‘stuffing’ techniques. The process of mapping (when multiplexing) and the subsequent de-mapping (when demultiplexing) of individual tributaries can introduce timing irregularities into a part of the datastream that constitutes the payload data.
In relation to the discrete-time aspects of SONET, timing irregularities associated with the process of mapping are known, and are referred to as “jitter”. SONET signals are therefore very “bursty”, i.e. the data stream can be transmitted in bursts interleaved by gaps of, for example, 3 bytes of redundant data.
Known solutions for reducing jitter employ a First-In-First Out (FIFO) buffer to smooth out transmitted SONET signals by equalising the gaps between units of data, such as bytes of the payload data. A FIFO buffer is typically a dual ported Random Access Memory (RAM) having a write-only port and a read-only port. Data-in having jitter, and therefore timing irregularities, is written into an available empty memory location and data is read out from the FIFO buffer in the order that the data was written in.
The data-out rate of the FIFO buffer is determined by a frequency of a read clock of the FIFO buffer. In effect, the FIFO buffer smoothes the flow of bits that arrive “early” or “late” due to the effects of the timing irregularities so as to achieve a desired constant flow of bits. The FIFO buffer subsequently resends the received bits with the correct timing based on a system clock. Since the function of the FIFO buffer is to maintain the read-out rate of data at as constant a rate as possible within the constraints of a discrete-time system, the FIFO buffer can be selected to receive data bursts of different widths, thereby accommodating, for example, both bit- and byte-wide architectures.
For efficient operation of the FIFO buffer, it is important to ensure that the FIFO buffer never over-fills or empties completely. Therefore despite the flow of data into the FIFO buffer being bursty, the flow of data out from the FIFO buffer must be controlled by the read clock so as to ensure that the data out is not only smooth and jitter free, but also controlled in a manner to ensure that the FIFO buffer is never full or empty. Preferably, the FIFO buffer is maintained at a midway point, i.e. half full. With knowledge of the mapping function employed, it is possible to calculate the minimum necessary depth of the FIFO buffer so as to ensure that no under- or over-flow events occur when the FIFO buffer is in a steady-state. It therefore follows that the read rate of the FIFO buffer needs to be carefully controlled.
A known solution for controlling the read clock frequency of a FIFO buffer employs a first order control loop apparatus coupled to the FIFO buffer. For each control loop period, the apparatus determines a depth error of the FIFO buffer. The depth of the FIFO buffer is defined in terms of the integer number of memory locations of the FIFO buffer being used at the time of measurement. The depth error of the FIFO buffer is defined as the difference between the depth of the FIFO buffer and the median point of the FIFO buffer. Hence, the range of possible depth errors is the range of positive and negative numbers relative to half the full depth of the FIFO buffer. If the FIFO buffer is determined to be close to capacity, the control loop apparatus initiates an increase in the read clock frequency of the FIFO buffer causing the rate of data leaving the FIFO buffer to increase. Conversely, if the depth of the FIFO buffer is determined to be close to empty, the control loop apparatus initiates a decrease in the read clock frequency of the FIFO buffer.
However, such known control loop apparatus can suffer from errors due to sampling if the frequency of the control loop is much less than the frequency of jitter in the incoming data stream written into the FIFO buffer. Therefore, on determining the depth of the FIFO buffer, it can take, for example, approximately 1 ms for the control loop apparatus to program a revised read clock frequency for the FIFO buffer so as to increase or decrease the flow of data out of the FIFO buffer as necessary. As such, if the depth of the FIFO buffer is read immediately after a payload has been written into the FIFO buffer and the control loop subsequently determines that the FIFO buffer is nearly full, the read clock frequency will be programmed so as to increase. However, during the time taken for the control loop apparatus to complete one period, the data-in flow rate may reduce significantly to a rate much less than the adjusted rate of data read out from the FIFO. Consequently, the FIFO buffer may empty (or, if the opposite occurs, fill) during the control loop period leading to an inefficient jitter reduction performance of the FIFO buffer.
According to a first aspect of the present invention, there is provided a control loop apparatus having a control loop period associated therewith and employing n-state logic, the apparatus comprising: a first processing element capable of acquiring data at a rate determined by a predetermined clock signal, the data corresponding to a parameter to be controlled; further processing elements arranged to generate, when in use, a control signal in response to the acquired data; wherein the control loop period, is a mathematical product of a period of the clock signal and a constant, the constant being the number of logic states of the n-state logic raised to a first integer power.
The first processing element may be further arranged to sum, or accumulate, the acquired data over a period of the control loop, thereby calculating an accumulated value. In particular, the first processing element and the further processing elements may be arranged to manipulate the bits constituting the accumulated value, thereby averaging the accumulated value over the period of the control loop.
The first processing element and the further processing elements may be arranged to shift the bits constituting the accumulated value, thereby averaging the accumulated value over the period of the control loop. Alternatively, the first processing element and the further processing elements may be arranged to truncate the bits constituting the accumulated value, thereby substantially averaging the accumulated value over the period of the control loop.
The further processing elements may be arranged to provide second order control.
The further processing elements may be arranged to calculate a rate of change of the accumulated value. In particular, the further processing elements may be arranged to apply a derivative gain to the calculated rate of change of the accumulated value. In one embodiment, the derivative gain corresponds to substantially the number of logic states raised to a second integer power.
The further processing elements may be arranged to apply a proportional gain to an average of the accumulated value, the average being over the control loop period. For example, the proportional gain, may correspond to substantially the number of logic states raised to a third integer power.
The parameter to be controlled may be a depth error of a First-In-First-Out (FIFO) buffer
The control signal may be used to control a period of a clocking signal
According to a second aspect of the present invention, there is provided in a control loop apparatus having a control loop period associated therewith and employing n-state logic, a method of operating the control loop apparatus, the method comprising the steps of: acquiring data at a rate determined by a predetermined clock signal, the data corresponding to a parameter to be controlled, generating a control signal in response to the acquired data; and setting the control loop period to be a mathematical product of a period of the clock signal and a constant, the constant being the number of logic states of the n-state logic raised to a first integer power
The method may further comprise the step of summing, or accumulating, the acquired data over a period of the control loop, thereby calculating an accumulated value. In particular, the method may further comprise the step of manipulating the bits constituting the accumulated value, thereby averaging the accumulated value over the period of the control loop.
The method may further comprise the step of shifting the bits constituting the accumulated value, thereby averaging the accumulated value over the period of the control loop. Alternatively, the method may further comprise the step of truncating the bits constituting the accumulated value, thereby substantially averaging the accumulated value over the period of the control loop.
The method may further comprise the step of providing second order control.
The method may further comprise the step of calculating a rate of change of the accumulated value. In particular, the method may further comprise the step of applying a derivative gain to the calculated rate of change of the accumulated value. For example, the derivative gain may correspond to substantially the number of logic states raised to a second integer power.
The method may further comprise the step of applying a proportional gain to an average of the accumulated value, the average being over the period of the control loop. In particular, the proportional gain may correspond to substantially the number of logic states raised to a third integer power.
The parameter to be controlled may be a depth error of a First-In-First-Out (FIFO) buffer.
The method may further comprise the step of using the control signal to control a period of a clocking signal.
It is thus possible to provide a control loop apparatus, and a method of controlling a read clock frequency, that are capable of supporting, in hardware, the speed of calculation required toy ensure that any hysteresis between the adaptation of the read clock frequency and the changes in the parameter to be controlled by the control loop apparatus is not detrimental to the control of the parameter. Consequently, in the context of controlling a depth error of a FIFO buffer, the control of the read clock frequency is sufficiently fast to follow sufficiently closely changes to the depth error. Further, by selecting integer powers of the number of states of logic, for example integer powers of 2, the input signal can be averaged in a computationally efficient manner through the use of bit-shifting techniques or truncation. The complexity of the hardware constituting the control loop apparatus is therefore simplified considerably. Additionally, the use of integer powers of the number of logic levels as weights also simplifies the hardware required in order to achieve multiplication. It is therefore possible to implement a second order control loop in hardware without the associated expected circuitry complexity to control the flow of high-speed data streams. Consequently, the cost of manufacture of the control loop apparatus is reduced.